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當(dāng)前位置 首頁 人才隊伍
  • 姓名： 鄭旭強
  • 性別： 男
  • 職稱： 研究員
  • 職務(wù)： 
  • 學(xué)歷： 博士
  • 電話： 82995939
  • 傳真： 
  • 電子郵件： zhengxuqiang@ime.ac
  • 所屬部門： 高頻高壓器件與集成研發(fā)中心
  • 通訊地址： 北京市朝陽區(qū)北土城西路3號

    簡　　歷：

  • 教育背景 

    2015-02--2018-06   University of Lincoln   獲博士學(xué)位 

    2006-09--2008-12   中南大學(xué)   獲碩士學(xué)位 

    2002-09--2006-07   中南大學(xué)   獲學(xué)士學(xué)位 

     

    工作簡歷 

    2021-04~現(xiàn)在, 中國科學(xué)院微電子所, 研究員 

    2018-07~2021-04,中科院微電子研究所, 副研究員 

    2010-10~2015-01,清華大學(xué), 集成電路設(shè)計工程師 

    社會任職：

  •  

    研究方向：

  • 高速串行接口SerDes 

    低抖動PLL時鐘發(fā)生器

    承擔(dān)科研項目情況：

  • 1、50G多通道中長距串行接口PHY電路設(shè)計與實現(xiàn)關(guān)鍵技術(shù)研究, 課題負責(zé)人, 重點研發(fā)計劃, 2019-08--2023-01 

    2、面向新一代400GbE數(shù)據(jù)傳輸?shù)某咚俅薪涌谛酒P(guān)鍵技術(shù)研究, 項目負責(zé)人, 自然科學(xué)基金面上項目, 2021-01--2024-12 

    3、高速 SerDes Tx 及無源信道 Bit-by-Bit 模塊建模技術(shù), 項目負責(zé)人, 橫向, 2020-03--2021-03  

    代表論著：

  • [1]    X. Zheng, H. Ding, F. Zhao, D. Wu, L. Zhou, J. Wu, F. Lv, J. Wang, X. Liu, “A 50-112-Gb/s PAM-4 Transmitter With a Fractional-Spaced FFE in 65-nm CMOS, ” IEEE J. Solid-State Circuits (JSSC), vol. 55, no. 7 pp. 1864 - 1876, Jul. 2020. 

    [2]   X. Zheng, F. Lv, L. Zhou, D. Wu, J. Wu, C. Zhang, W. Rhee, and X. Liu, “Frequency-domain modeling and analysis of injection-locked oscillators,” IEEE J. Solid-State Circuits (JSSC), vol. 55, no. 8, pp. 1651 - 1664, Jun. 2020. 

    [3]      H. Wang, J. Peng, X. Zheng, and S. Yue, “A robust visual system for small target motion detection against cluttered moving backgrounds,” IEEE Trans. on Neural Networks and Learning Systems (TNNL), vol. 31, no. 3, pp. 839 - 853, March 2020. 

    [4]    H. Ding, X. Zheng, D. Wu, L. Zhou, J. Wu, F. Lv, J. Wang, and X. Liu, “A 112-Gb/s PAM-4 transmitter with a 2-tap fractional-spaced FFE in 65-nm CMOS,” in Proc. IEEE European Solid-State Circuits Conf. (ESSCIRC), IEEE Solid-State Letters. (SSCL), vol. 2, no. 9, pp. 195-198, Sep. 2019.

    [5]    X. Zheng, C. Zhang, and F. Lv et al., “A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS,” IEEE J. Solid-State Circuits (JSSC), vol. 52, no. 11, pp. 2963-2978, Nov. 2017. 

    [6]    X. Zheng, C. Zhang, and F. Lv et al.,“A 4-40 Gb/s PAM4 transmitter with output linearity optimization in 65 nm CMOS,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), Apr. 2017. 

    [7]   X. Zheng, F. Lv, and F. Zhao et al.,“A 10 GHz 56 fsrms-integrated-jitter and -247 dB FOM ring-VCO based injection-locked clock multiplier with a continuous frequency-tracking loop in 65 nm CMOS,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), Apr. 2017. 

    [8]    X. Zheng, C. Zhang, and S. Yuan et al., “An improved 40 Gb/s CDR with jitter-suppression filters and phase-compensating interpolators,” in Proc. IEEE Asian Solid-State Circuits Conf. (ASSCC), Nov. 2016, pp. 85-88. 

    [9]   X. Zheng, C. Zhang, and F. Lv et al., “A 5-50 Gb/s quarter rate transmitter with a 4-tap multiple-MUX based FFE in 65 nm CMOS,” in Proc. IEEE European Solid-State Circuits Conf. (ESSCIRC), Sep. 2016, pp. 305-308. 

    [10]  X. Zheng, Z. Wang, and F. Li et al., “A 14-bit 250 MS/s IF sampling pipelined ADC in 180 nm CMOS process,” IEEE Trans. Circuits Syst. I, Reg. Papers (TCAS-I), vol. 63, no. 9, pp. 1381-1392, Sep. 2016.

    專利申請：

    獲獎及榮譽：

  •  2020年度中科院微電子研究所十佳先進工作者。