教育背景
2007-2011：中國科學院微電子研究所，微電子學與固體電子學專業(yè)，工學博士
2004-2007：遼寧大學物理學院，微電子學與固體電子學專業(yè)，理學碩士
2000-2004：遼寧大學物理學院，電子科學與技術專業(yè)，工學學士
工作簡歷
2018年-至今：中國科學院微電子研究所，集成電路先導工藝研發(fā)中心，正高級工程師，博士導師，入選中科院“院級高層次引進人才”，從事亞10納米三維器件與集成技術研究
2011-2017年：新加坡聯(lián)華電子公司（UMC），主任工程師，從事納米CMOS器件和集成技術研究，主要負責邏輯產(chǎn)品、SRAM Macro以及eHV制程研發(fā)和平臺建設
1. 2018年，02專項子課題“鍺/鍺硅高遷移率溝道三維器件及關鍵共性技術”，核心骨干
2. 2019年，中國科學院“集成電路新器件與先導工藝”課題，子課題負責人
3. 2019年，北京市科委“水平堆疊環(huán)柵器件研制與新型溝道原型器件研究”課題，課題負責人
4. 2019年，中科院微電子所所長基金“SiGe高遷移率溝道FinFET集成技術研究”，課題負責人
5. 2020年，北京市自然基金面上項目“鍺硅高遷移率溝道FinFET器件關鍵集成技術研究”，項目負責人
6. 2021年，國家自然科學基金面上項目“適用于三維FinFET器件的高濃度鍺硅高遷移率溝道制備和鈍化技術及機理研究”，項目負責人
1. Zhiqian Zhao, Yongliang Li*, Shihai Gua, et al., High crystal quality strained Si0.5Ge0.5 layer with a thickness of up to 50 nm grown on the three-layer SiGe strain relaxed buffer. Materials Science in Semiconductor Processing, 2019, 99,159
2. Zhiqian Zhao, Yongliang Li*, Guilei Wang, et al., A novel three-layer graded SiGe strain relaxed buffer for the high crystal quality and strained Si0.5Ge0.5 layer epitaxial grown. Journal of Materials Science: Materials in Electronics, 2019, 30, 14130
3. Zhiqian Zhao, Yongliang Li*, Guilei Wang, et al., Process optimization of the Si0.7Ge0.3 Fin Formation for the STI first scheme. Semicond. Sci. Technol., 2019, 34, 125008
4. Zhiqian Zhao, Xiaohong Cheng, Yongliang Li*, et al., Investigation on the formation technique of SiGe Fin for the high mobility channel FinFET device. Journal of Materials Science: Materials in Electronics, 2020, 31(8),5854
5. Yongliang Li, Xiaohong Cheng, Zhaoyang Zhong, et al., Key Process Technologies for Stacked Double Si0.7Ge0.3 Channel Nanowires Fabrication. ECS Journal of Solid State Science and Technology, 2020, 9, 064009
6. Xiaohong Cheng, Yongliang Li*, Guilei Wang, et al., Investigation on thermal stability of Si0.7Ge0.3/Si stacked multilayer for gate-all-around MOSFETS. Semicond. Sci. Technol., 2020, 35(11), 115008-1-5
7. Xiaohong Cheng, Yongliang Li*, Haoyan Liu, et al., Selective wet etching in fabricating SiGe nanowires with TMAH solution for gate-all-around MOSFETs. Journal of Materials Science: Materials in Electronics, 2020, 31, 22478
8. Haoyan Liu, Yongliang Li*, Xiaohong Cheng, et al., Fabrication and selective wet etching of Si0.2Ge0.8/Ge multilayer for Si0.2Ge0.8 channel gate-all-around MOSFETs. Materials Science in Semiconductor Processing, 2021, 121, 105397
9. Yongliang Li, Fei Zhao, Xiaohong Cheng, et al., Four-Period Vertically Stacked SiGe/Si Channel FinFET Fabrication and Its Electrical Characteristics. Nanomaterials, 2021, 11(7), 1689
10. Yongliang Li, Fei Zhao, Xiaohong Cheng, et al., Integration of Si0.7Ge0.3 fin onto a bulk-Si substrate and its P-type FinFET device fabrication. Semicond. Sci. Technol. 2021, 36, 125001
已授權專利：
1. 李永亮，王文武，一種半導體結構及其制備方法，授權公告號：CN 109003902 B
2. 李永亮，程曉紅等，一種堆疊納米線或片CMOS器件制備方法，授權公告號：CN 110729248 B
3. Yongliang Li, Xiaohong Cheng. SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME, 授權公告號: US11024708 B1.
4. Yongliang Li, Qiuxia Xu. Method for etching Mo-based metal gate stack with Aluminium nitride barrier, 授權公告號: US20110263114.
5. Qiuxia Xu, Yongliang Li. Manufacturing method for structure of metal gate/ high k gate dielectric stack layer，授權公告號US20110256704.
6. Qiuxia Xu, Yongliang Li. Method for manufacturing metal gate stack structure in gate-first process, 授權公告號：US20120003827.
7. Qiuxia Xu, Yongliang Li, Gaobo Xu. Method for manufacturing CMOS FET, 授權公告號： US20130078773.
8. Qiuxia Xu, Yongliang Li. Method for manufacturing a metal gate electrode/high K dielectric gate stack，授權公告號：US20110256704.
9. Qiuxia Xu, Yongliang Li. Method for removing polymer after etching gate stack structure of high-k gate dielectric/metal gate, 授權公告號：US8334205.
10. 李永亮, 徐秋霞,一種選擇性去除TaN金屬柵材料的方法，授權公告號：CN101656208 A.
中科院微電子所優(yōu)秀員工一次
中國科學院院長優(yōu)秀獎一次
中國科學院朱李月華獎一次
人才隊伍