教育背景
2017.08–2021.06:澳門大學(xué),電機(jī)及電腦工程,博士
2014.09–2017.07:中國(guó)科學(xué)院大學(xué),電子與通信工程,碩士
2010.09–2014.07:青島大學(xué),微電子學(xué),學(xué)士
工作簡(jiǎn)歷
2023.06–至今:中國(guó)科學(xué)院微電子研究所,研究員,課題組長(zhǎng)
2023.04–2023.06:中國(guó)科學(xué)院微電子研究所,副研究員,課題組長(zhǎng)
2021.07–2023.03:東京大學(xué),特任研究員
模擬、射頻、混合信號(hào)集成電路設(shè)計(jì)
硅基射頻、毫米波、太赫茲通信芯片設(shè)計(jì)
硅基壓控振蕩器、鎖相環(huán)、收發(fā)機(jī)芯片設(shè)計(jì)
功率放大器、低噪聲放大器、濾波器等射頻前端電路設(shè)計(jì)
1、國(guó)家青年人才項(xiàng)目,項(xiàng)目負(fù)責(zé)人,2024.01–2026.12
2、中國(guó)科學(xué)院青年人才項(xiàng)目,項(xiàng)目負(fù)責(zé)人,2024.01–2026.12
3、所長(zhǎng)基金項(xiàng)目,項(xiàng)目負(fù)責(zé)人,2023.01–2025.12
論文
[1]?Masaru Osada, Zule Xu, Zunsong Yang, and Tetsuya Iizuka, "A Fractional-N Ring PLL Using Harmonic-Mixer-Based Dual Feedback and Split-Feedback Frequency Division with Phase-Domain Filtering," IEEE Journal of Soli-State Circuits (JSSC), 2024.
[2]?Yunbo Huang, Yong Chen, Zunsong Yang, Rui P. Martins, and Pui-In Mak, "A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and ?74.2dBc Reference Spur," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, Feb. 2024.
[3]?Zunsong Yang, Yong Chen, Shiheng Yang, Pui-In Mak and Rui P. Martins, "A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving ?252.9dB Jitter-Power FoM And ?63dBc Reference Spur," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, pp. 270-272, Feb. 2019.
[4]?Zunsong Yang, Masaru Osada, Shuowei Li, Yuyang Zhu, and Tetsuya Iizuka, "A Reference-Sampling PLL with Low-Ripple Double-Sampling PD Achieving ?80-dBc Reference Spur and ?259-dB FoM with 12-pF Input Load," IEEE Symposium on VLSI Technology and Circuits (VLSI), Kyoto, Japan, June 2023.
[5]? Zunsong Yang, Zule Xu, Masaru Osada and Tetsuya Iizuka, "A 10-GHz Inductorless Cascaded PLL with Zero-ISF Sub-Sampling Phase Detector Achieving ?63-dBc Reference Spur, 175-fs RMS Jitter And ?240-dB FOMjitter," IEEE Symposium on VLSI Technology and Circuits (VLSI), Hawaii, USA, pp. 10-11, June 2022.
[6]?Zunsong Yang, Yong Chen, Pui-In Mak and Rui P. Martins, "A 0.003-mm2 440fsRMS-Jitter and ?64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS," IEEE Asian Solid-State Circuits Conference (A-SSCC), Macau, pp. 283-284, Nov. 2019.
[7]?Zunsong Yang, Yong Chen, Pui-In Mak and Rui P. Martins, "A 0.003-mm2 440fsRMS-Jitter and ?64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS," IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), vol. 68, no. 6, pp. 2307-2316, June 2021.
[8]?Zunsong Yang, Yong Chen, Pui-In Mak and Rui P. Martins, "A Calibration-Free, Reference-Buffer-Free, Type-I Narrow-Pulse-Sampling PLL with ?78.7-dBc REF Spur, ?128.1-dBc/Hz Absolute In-Band PN and ?254-dB FOM," IEEE Solid-State Circuits Letters (SSC-L), vol. 3, pp. 494-497, Oct. 2020.
[9]?Zunsong Yang, Yong Chen, Jia Yuan, Pui-In Mak and Rui P. Martins, "A 3.3-GHz Integer-N Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push-Pull SS-PD and a Fast-Locking FLL Achieving ?82.2-dBc REF Spur and ?255-dB FOM," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 30, no. 2, pp. 238-242, Feb. 2022.
書籍/章節(jié)
Hao Guo, Zunsong Yang, Chee Cheow Lim, Harikrishnan Ramiah, Yatao Peng, Yong Chen, Jun Yin, Pui-In Mak & Rui P. Martins, Power-Efficient RF and mm-Wave VCOs/PLL, in Mixed-Signal Circuits in Nanoscale CMOS, Analog Circuits and Signal Processing, Springer, 2023.
國(guó)家海外高層次人才引進(jìn)計(jì)劃入選者
中國(guó)科學(xué)院高層次人才引進(jìn)計(jì)劃入選者
人才隊(duì)伍