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后摩爾EDA器件模型與集成設(shè)計(jì)方法研究

1. 前沿器件緊湊模型與AI驅(qū)動(dòng)建模算法設(shè)計(jì)

2. 關(guān)鍵器件物理：可靠性機(jī)理與傳輸機(jī)理研究

3. 異質(zhì)集成芯片設(shè)計(jì)與EDA-D/STCO方法

1）國(guó)家重點(diǎn)研發(fā)計(jì)劃課題, 2021YFB3600704，在研，主持（2021-2025）

2)?國(guó)家高層次青年人才項(xiàng)目, 在研，主持（2022-2024）

3）國(guó)家自然科學(xué)基金委員會(huì)面上項(xiàng)目，62274178，在研，主持（2023-2026）

4) 集成電路先進(jìn)器件工藝仿真與智能EDA青年交叉團(tuán)隊(duì)， JCTD-2022-07, 在研，參與（2023-2025）

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[2] Lihua Xu, Kaifei Chen, Zhi Li, Jingrui Guo, Linfang Wang, Yue Zhao, Shijie Huang, Zhidao Zhou, Chunmeng Dou*, Guanhua Yang*, Lingfei Wang*, Ling Li and Ming Liu. "Reliability-Aware Ultra-Scaled IDG-InGaZnO-FET Compact Model to Enable Cross-layer Co-design for Highly Efficient Analog Computing in 2T0C-DRAM"[C]//2023 International Electron Devices Meeting (IEDM). IEEE.??

[3] Tiancheng Gong, Lihua Xu, Wei Wei, Pengfei Jiang, Peng Yuan, Bowen Nie, Yuanquan Huang, Yuan Wang, Yang Yang, Jianfeng Gao, Junfeng Li, Jun Luo, Lingfei Wang*, Jianguo Yang*, Qing Luo*, Ling Li, Steve S Chung, Ming Liu, "First Demonstration of a Design Methodology for Highly Reliable Operation at High Temperature on 128kb 1T1C FeRAM Chip", in 2023 Symposium on VLSI Technology, IEEE, 2023.????

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[6] Jingrui Guo, Kaizhen Han, Subhali Subhechha, Xinlv Duan, Qian Chen Di Geng, Shijie Huang, Lihua Xu, Junjie An, Gouri Sankar Kar, Xiao Gong, Lingfei Wang*, Ling Li*, Ming Liu, "A New Surface Potential and Physics Based Compact Model for a-IGZO TFTs at Multinanoscale for High Retention and Low-Power DRAM Application", in 2021 IEEE International Electron Devices Meeting (IEDM), 2021, pp. 8.5. 1-8.5. 4.?????

[7] Ying Zhao，Lingfei Wang*, Zhenhua Wu, Franz Schanovsky Xiaoxin Xu, Hong Yang, Hao Yu, Jinru Lai, Donyang Liu, Xichen Chuai, Yue Su, Xingsheng Wang, Ling Li* and Ming Liu*. "A Unified Physical BTI Compact Model in Variability-Aware DTCO Flow: Device Characterization and Circuit Evaluation on Reliability of Scaling Technology Nodes," in 2021 Symposium on VLSI Technology, pp. 1-2. IEEE, 2021.????

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