3D integration using TSVs is a promising method to achieve further improvements for future electronic systems. Stress is induced in silicon near the TSV by CTE mismatch between filling copper and Silicon substrate. When the substrate is an active one, this stress will influence the performance of the devices fabricated therein. To understand the induced stress and its impact on device performance deeply, this paper gives a comprehensive study. Orthotropic feature of silicon is considered to calculate the stress profile in silicon in vicinity of the Cu TSV. The saturation drain current variation of MOSFETs is calculated from the simulated stress data using piezoelectric effect theory. The results can well match the reported measuring data, giving an effective method to deeply understand the TSV induced stress and its impact on device performance.
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